This invention concerns multi-core data processing systems. It is typical in such multi-core systems for each core to have its own local cache memory and for all the cores to share a common higher level memory. This could be a memory on the same integrated circuit as the multiple cores (on chip) or an external memory (off chip). In such a multi-core data processing system more than one core may write to the same higher level memory. A multi-core shared memory controller must coordinate memory traffic between the multiple cores and the shared memory.
This task includes contrary goals of maintaining coherence and suitable memory access latency. Each time one of the multiple cores updates a cache entry corresponding to an address in shared memory, the multi-core shared memory controller must insure that other cores operate upon the latest version of the data. Conflicts may occur if the data is cached by more than one core. The prior art typically handles this by a snoop cycle. The multi-core shared memory controller polls (snoops) the caches of other cores to determine whether they store the address of interest. The response may be no, the cache doesn't store the data. Upon a yes response, meaning the cache stores the data, the remote cache determines if its cache data is dirty. A dirty cache entry is one that has been updated locally since the last update to the shared memory. If the remote cache entry is clean, then it signals the multi-core shared memory controller. This situation presents no conflict with the operation triggering the snoop. If the remote cache entry is dirty, the multi-core shared memory controller must reconcile the data stored in the two (or more) caches. It is possible that the separate caches have updated the same cache line but not the same data. In this case the dirty portion of the cache lines should be merged before writing to the shared memory. If the separate caches updated the same date, they need to be written to the shared memory in proper order to maintain coherence.